By Arthur Ed LeBouthillier

This article appeared in the January 2000 issue of The Robot Builder.

Mobile computing applications have different demands than in the desktop realm. Because a desktop computer is fed from a
wall socket, it can be designed to use large amounts of power as if it were an infinite resource. Desktop computers can also be built to operate with IC’s that generate lots of heat because designers can add large fans. In fact, some recent desktop computers have two fans inside: one for the power supply and one fan dedicated to cooling off the processor. Mobile  computers, however, do not have the luxuries that desktop machines have. They must be efficient in their power use because they usually run from batteries and they can’t generate too much heat because to be portable, they must be small.

Small handheld or laptop computers are generally not designed with fans yet they cannot get so hot that they damage
components or become uncomfortable for their users. Mobile robots fall under the category of mobile computing and it is
worth examining new developments for mobile computing that might show their way in mobile robots. One very recent
development in mobile processors has been the Crusoe microprocessor by Transmeta. It offers a glimpse into mobile current computing trends.

The Crusoe Family of Mobile Processors

In the past few years, we have seen a trend towards reduced instruction set computers (RISC). These processors use simple
instructions which run in one computer clock cycle. Transmeta is a new microprocessor company which has entered the  mobile processor market. In a recently much-hyped product release, they announced a new family of microprocessors specifically targeted for mobile computing applications. This family evidences a wide array of newer computing technologies packaged together to create lower-power demands in a very fast processor. The unique features of these processors are worth examining. First off, the Crusoe family of processors implements a kind of parallelism.  Second, the Crusoe family of processors is designed to be low power, making them more suitable for mobile processing applications. Third, the Crusoe family of processors is meant to execute the x86 instruction set as used Pentium-class processors.

Crusoe Parallelism

The Crusoe family of microprocessors breaks the trend in using RISC processors. Rather than using simple, RISC-like  features as we have seen among a number of current processors, the Crusoe family of processors utilizes Very Long Instruction Word (VLIW) techniques. VLIW processors have large instruction words which contain a number of smaller instructions which can be made to run in parallel. A typical Crusoe instruction consists of four 32-bit instruction words which run in parallel. The advantage of this is obvious: four operations can be performed simultaneously.

 A single 128-bit multi-instruction is known as a molecule and it consists of four atomic instructions. The 128-bit instruction’s four 32-bit words are each instructions for different processing elements within the processor: the Floating Point Unit (FPU) which performs math operations on decimal numbers, the Integer Unit which performs math operations on integers, the Load/Store Unit which takes information to or from memory and the Branch Unit which controls program flow. Therefore, at  one moment, a Crusoe processor can add a floating point number, add integers, save something to memory and jump to another location in the program.

Crusoe’s Low Power Technology

The Crusoe processor utilizes several techniques to lower power consumption substantially from that of Pentium-class machines. The most significant way that this is done is by not trying to implement the Pentium design at all. The structure and design of the Crusoe processor are actually very different from that of the Pentium’s. Crusoe processors have been designed from the beginning to be extremely power efficient by having a very low number of transistors in their design. A similar-powered Crusoe processor has about half of the die area of the equivalent Pentium processor. Another power-saving technique used is that processor speed and voltages are adjusted dynamically to give optimum power usage at any instant. Since power demands are linear with respect to processor speed and by the square of the voltage used, there can be a cubic reduction in power by selecting the proper voltage and processor speed.

Implementing Pentium Instructions

Rather than trying to duplicate all of the instructions of the Pentium processor, the Crusoe chips utilize an ingenious software technique called Code Morphing to implement a Pentium in software. Code Morphing provides a dynamic run-time compiler which converts x86 instructions into Crusoe instructions on the fly. This would normally be an extremely slow operation of analyzing and recompiling a program on the fly, but the Crusoe processors save the compiled code and operate from a different code storage area. Therefore, when an x86 program is run, each block is compiled into Crusoe instructions as it is called. Once a block of code has been compiled, the Crusoe processor can use that pre-compiled block in future calls to that
code section. This means that once a code section has been compiled, it can be run at full Crusoe speed without recompiling.

This ingenious technique allows a Crusoe processor to run x86 code at high speed but without actually implementing all hardware of a Pentium. Of course, there is a penalty for translating the x86 instructions the first time, but once compiled, the program runs at competitive rates but with much less power. Based on benchmarks provided by Transmeta, it appears as if a Pentium-class Crusoe runs with about ¼ the power and heat. Trends Evident in the Crusoe
By itself, the Crusoe is a nice processor for embedded applications. It also seems to illustrate a trend in modern processor design. The first aspect of this trend is the parallelism evidenced by the VLIW design. Several processors have used techniques similar to this. The Pentium itself breaks an x86 instruction into a number of micro-operations that can run in parallel. Texas Instrument’s C6000 DSP used the VLIW technique allowing it to perform substantially faster than other
DSP’s. Now, the Crusoe is using VLIW techniques to allow more parallelism.

Another technology trend that seems obvious is the importance of smart compiler technology. A number of DSP companies have begun producing their own compilers rather than letting third-party developers do it because they are stressing compiler technology as vital to exploiting the full capabilities of their processors. Java was also part of this trend by prompting a desire for JIT (just-in-time) compilers which converted Java code into machine code at run time. Now with the Crusoe processors, we’re seeing a smart compiler performing the function of code conversion and optimization in order to replace hardware. If anything, the Crusoe processors could not enter into the x86-compatible market without the existence of the run-time compiling used in Code Morphing.

Finally, one other trend that seems to be obvious is recognized by the term “post-PC era.” We are now entering an era where powerful portable computers are becoming very important. This contrasts with the last era where desktop computers reigned
without peer and the era prior to that where mainframes were the most important computing environment. In the post-PC environment, capable mobile computers will become more widely used.

The arrival of processors like the Crusoe signals this trend where capable, low-power mobile processors are in demand. Of course this demand did not immediately arrive, but now a whole company has arrived into the PC class processor market whose sole-emphasis has been on getting lower-power with higher processor speed.